Various interfaces can be used to communicate between a controller and a memory of a storage system. One such interface is the Toggle Mode Double Data Rate (DDR) interface. Toggle Mode DDR works by generating input/output (I/O) signals applied on the write enable and read enable inputs on both the rising and the falling edge of a clock signal provided to the memory by the controller. To provide a desired margin of signal integrity and data transfer performance, some controllers are designed to provide a clock signal with a duty cycle at or near 50%. However, due to various distortions in the clock signal path, the duty cycle of the clock signal may be altered. To address this, simulations can be run during the design phase with models of the controller and the clock signal path to determine the parasitics that introduce duty cycle distortion. Based on the simulations, optimum drive strengths of input-output (“IO”) drivers can be selected and different duty cycle distortion budgets can be assigned to different components in the clock signal path.